The present invention relates generally to forming a contact structure and a capacitor structure, and more particularly to forming a contact structure and a capacitor container structure for high-density memory arrays.
Advances in miniaturization of integrated circuits have led to smaller areas available for devices such as transistors and capacitors. For example, in semiconductor manufacture of a memory array for a dynamic random access memory (DRAM), each memory cell comprises a capacitor, a contact, and a transistor. In a conventional DRAM, pairs of memory cells are located within regions (xe2x80x9cmemory cell areasxe2x80x9d) defined by intersecting row lines (xe2x80x9cword linesxe2x80x9d) and column lines (xe2x80x9cbit linesxe2x80x9d or xe2x80x9cdigit linesxe2x80x9d). Accordingly, to increase memory cell density of the memory array, row lines and column lines are positioned with minimal spacing (xe2x80x9cpitchxe2x80x9d). Using minimal pitch in turn constrains memory cell area.
To increase capacitance without increasing memory cell area, the DRAM industry has shifted from planar capacitor structures (e.g., xe2x80x9cparallel plate capacitorsxe2x80x9d) to vertical capacitor structures (e.g., xe2x80x9ccontainer capacitorsxe2x80x9d). As suggested by its name, a xe2x80x9ccontainer capacitorxe2x80x9d in may be envisioned as two cup-shaped electrodes, one at least partially stacked within the other, separated by a dielectric layer or layers. Accordingly, container capacitor electrodes provide more common surface area within a memory cell area than its planar counterpart, and thus, container capacitors do not have to occupy as much memory cell area as their planar counterparts in order to provide an equivalent capacitance.
However, in a high-density memory array architecture (by high-density memory array architecture, it is meant a memory array with a bit line-to-bit line pitch equal to or less than 0.5 microns), there is little space to form container capacitor structures and associated contact structures. More particularly, in a high-density memory array architecture, gaps between contacts and container capacitor bottom electrodes are about 200 nm or less, and gaps between adjacent container capacitor bottom electrodes are about 620 nm or less.
Thus, it is difficult to deposit container capacitor dielectric and top electrode layers without interfering with formation of one or more contact structures. Moreover, while not wishing to be bound by theory, it is believed that owing to stress migration and nearness between a container capacitor top electrode and one or more contact plugs, electrical shorting between the two may result.
Thus, there is a need in the art to provide a method of forming a contact structure and a container capacitor structure that may be used in forming a high-density memory array.
Accordingly, the present invention provides a method for forming at least a portion of a capacitor electrode and at least a portion of a contact plug, as well as providing devices resulting therefrom. One exemplary embodiment provides a method in which at least a portion of a top electrode of a container capacitor and a contact plug are formed in a common deposition step. In a more specific exemplary process embodiment, the deposition forms the top electrode on the interior of the container capacitor bottom electrode. In an alternate embodiment, the deposition forms the top electrode on the interior and exterior of the container capacitor bottom electrode. In yet another exemplary embodiment, the exterior part of the top electrode is formed only on a portion of the bottom electrode facing away from the contact plug. Exemplary apparatus embodiments include cells having a container capacitor, a plug capacitor, or other vertical or at least non-planar capacitors. Exemplary embodiments such as these are particularly well-suited for use in forming high-density memory arrays.